Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment

Ryotaro Sakai, Naru Sugimoto, Hideharu Amano, Takaaki Miyajima, Naoyuki Fujita

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Hall thruster is a sort of electric propulsion and has been studied in many research institutes. In the design process of Hall thruster, a numerical simulation called Full-PIC (Particle-In-Cell) method is used. Although this simulation provides high accurate result, it is known as a very time consuming job. In this paper, we present a study of acceleration of Full-PIC simulation on a CPU-FPGA tightly coupled environment. A high-load part is selected and off-loaded to an FPGA. Zynq-7000 and Vivado HLS are used for implementation. To optimize the implemented design, every target process was divided into some parts for pipelining and adjustment interval. Three off-loaded subroutines named "field-source", "particle-att-ion" and "particle-att-ele" achieved 8.53 times, 12.78 times and 14.95 times performance compared with the software execution, respectively. The total execution time of target part is sped up 5.17 times compared with Cortex-A9 667MHz in Zynq.

本文言語English
ホスト出版物のタイトルProceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016
出版社Institute of Electrical and Electronics Engineers Inc.
ページ8-14
ページ数7
ISBN(電子版)9781509035304
DOI
出版ステータスPublished - 2016 12月 5
イベント10th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016 - Lyon, France
継続期間: 2016 9月 212016 9月 23

Other

Other10th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016
国/地域France
CityLyon
Period16/9/2116/9/23

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ

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