Advanced ATM-layer function MCM-D module for ATM wide-area network

Tomoaki Kawamura, Naoaki Yamanaka, Katsumi Kaizu

研究成果: Conference contribution

3 引用 (Scopus)

抄録

This paper describes a high-performance and cost-effective MCM-D module for an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size was reduced to 50.8 mm×50.8 mm. This is 40% of that (100 mm×65 mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a high-performance ASIC with high-speed (access time 20 ns) and large-capacity (1 MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module was mounted on an ATM line interface circuit, and realized 150 Mbit/s throughput ATM-layer functions(header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM-WAN (wide-area network) switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to ATM-WAN switching systems and future B-ISDN ATM switching systems.

元の言語English
ホスト出版物のタイトルProceedings - Electronic Components and Technology Conference
編集者 Anon
出版者IEEE
ページ486-490
ページ数5
出版物ステータスPublished - 1997
外部発表Yes
イベントProceedings of the 1997 47th IEEE Electronic Components & Technology Conference - San Jose, CA, USA
継続期間: 1997 5 181997 5 21

Other

OtherProceedings of the 1997 47th IEEE Electronic Components & Technology Conference
San Jose, CA, USA
期間97/5/1897/5/21

Fingerprint

Wide area networks
Automatic teller machines
Multicarrier modulation
Switching systems
Static random access storage
Random access storage
Application specific integrated circuits
Packaging
Voice/data communication systems
Substrates
Computer hardware
Interfaces (computer)
Field programmable gate arrays (FPGA)
Throughput
Data storage equipment
Networks (circuits)
Monitoring

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Kawamura, T., Yamanaka, N., & Kaizu, K. (1997). Advanced ATM-layer function MCM-D module for ATM wide-area network. : Anon (版), Proceedings - Electronic Components and Technology Conference (pp. 486-490). IEEE.

Advanced ATM-layer function MCM-D module for ATM wide-area network. / Kawamura, Tomoaki; Yamanaka, Naoaki; Kaizu, Katsumi.

Proceedings - Electronic Components and Technology Conference. 版 / Anon. IEEE, 1997. p. 486-490.

研究成果: Conference contribution

Kawamura, T, Yamanaka, N & Kaizu, K 1997, Advanced ATM-layer function MCM-D module for ATM wide-area network. : Anon (版), Proceedings - Electronic Components and Technology Conference. IEEE, pp. 486-490, Proceedings of the 1997 47th IEEE Electronic Components & Technology Conference, San Jose, CA, USA, 97/5/18.
Kawamura T, Yamanaka N, Kaizu K. Advanced ATM-layer function MCM-D module for ATM wide-area network. : Anon, 編集者, Proceedings - Electronic Components and Technology Conference. IEEE. 1997. p. 486-490
Kawamura, Tomoaki ; Yamanaka, Naoaki ; Kaizu, Katsumi. / Advanced ATM-layer function MCM-D module for ATM wide-area network. Proceedings - Electronic Components and Technology Conference. 編集者 / Anon. IEEE, 1997. pp. 486-490
@inproceedings{6b166385e18f4e32bbb87350ce7d312c,
title = "Advanced ATM-layer function MCM-D module for ATM wide-area network",
abstract = "This paper describes a high-performance and cost-effective MCM-D module for an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size was reduced to 50.8 mm×50.8 mm. This is 40{\%} of that (100 mm×65 mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a high-performance ASIC with high-speed (access time 20 ns) and large-capacity (1 MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module was mounted on an ATM line interface circuit, and realized 150 Mbit/s throughput ATM-layer functions(header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM-WAN (wide-area network) switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to ATM-WAN switching systems and future B-ISDN ATM switching systems.",
author = "Tomoaki Kawamura and Naoaki Yamanaka and Katsumi Kaizu",
year = "1997",
language = "English",
pages = "486--490",
editor = "Anon",
booktitle = "Proceedings - Electronic Components and Technology Conference",
publisher = "IEEE",

}

TY - GEN

T1 - Advanced ATM-layer function MCM-D module for ATM wide-area network

AU - Kawamura, Tomoaki

AU - Yamanaka, Naoaki

AU - Kaizu, Katsumi

PY - 1997

Y1 - 1997

N2 - This paper describes a high-performance and cost-effective MCM-D module for an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size was reduced to 50.8 mm×50.8 mm. This is 40% of that (100 mm×65 mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a high-performance ASIC with high-speed (access time 20 ns) and large-capacity (1 MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module was mounted on an ATM line interface circuit, and realized 150 Mbit/s throughput ATM-layer functions(header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM-WAN (wide-area network) switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to ATM-WAN switching systems and future B-ISDN ATM switching systems.

AB - This paper describes a high-performance and cost-effective MCM-D module for an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size was reduced to 50.8 mm×50.8 mm. This is 40% of that (100 mm×65 mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a high-performance ASIC with high-speed (access time 20 ns) and large-capacity (1 MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module was mounted on an ATM line interface circuit, and realized 150 Mbit/s throughput ATM-layer functions(header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM-WAN (wide-area network) switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to ATM-WAN switching systems and future B-ISDN ATM switching systems.

UR - http://www.scopus.com/inward/record.url?scp=0030653548&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030653548&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0030653548

SP - 486

EP - 490

BT - Proceedings - Electronic Components and Technology Conference

A2 - Anon, null

PB - IEEE

ER -