Advantages of densely packed multi-wire transistors with planar gate structure fabricated on low-k buried insulator over planar silicon-on-insulator devices

Mizuki Ono, Ken Uchida, Tsutomu Tezuka

    研究成果: Article査読

    抄録

    In this paper, electrical characteristics of densely packed multi wire transistors with a planar gate structure are systematically investigated using three-dimensional device simulations in terms of dependences of threshold voltage roll-off and current drivability on a channel width, height, and distance. The simulation results revealed that densely packed multi wire transistors with a planar gate structure have advantages over planar silicon-on-insulator (SOI) devices in terms of both threshold voltage roll-off characteristics and current drivability. It is shown that narrowing a width and lowering a height of channels are effective for improvement in both threshold voltage roll-off characteristics and current drivability and that shrinking a distance between channels is effective for improvement in current drivability although it degrades threshold voltage roll-off characteristics. It is also shown that lowering a dielectric constant of a buried insulator below wires is effective for improvement in both threshold voltage roll-off characteristics and current drivability of wire transistors.

    本文言語English
    ページ(範囲)545051-545056
    ページ数6
    ジャーナルJapanese journal of applied physics
    48
    5
    DOI
    出版ステータスPublished - 2009 5月 1

    ASJC Scopus subject areas

    • 工学(全般)
    • 物理学および天文学(全般)

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