An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept

Peter Toth, Hiroki Ishikuro

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

This paper presents a wide-dynamic-range high-resolution timedomain converter concept tailored for low-power sensor interfaces. The unique system structure applies different techniques to reduce circuit complexity, power consumption, and noise sensitivity. A multi-cycle concept allows a virtual delay line extension and is applied to achieve high resolution down to 1ns. At the same time, it expands the dynamic range drastically up to 2.35 ms. Moreover, individually tunable delay elements in the range of 1ns to 12 ns allow on-demand flexible operation in a low- or high-resolution mode for smart sensing applications and flexible power control. The concept of this paper is evaluated by a custom-designed FPGA supported PCB. The presented concept is highly suitable for onchip integration.

本文言語English
ホスト出版物のタイトルProceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
出版社Institute of Electrical and Electronics Engineers Inc.
ページ105-106
ページ数2
ISBN(電子版)9781450379991
DOI
出版ステータスPublished - 2021 1 18
イベント26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 - Virtual, Online, Japan
継続期間: 2021 1 182021 1 21

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
国/地域Japan
CityVirtual, Online
Period21/1/1821/1/21

ASJC Scopus subject areas

  • 電子工学および電気工学
  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計

フィンガープリント

「An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル