An 8 bit 0.3-0.8 v 0.2-40 MS/s 2-bit/Step SAR ADC with successively activated threshold configuring comparators in 40 nm CMOS

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

研究成果: Article査読

18 被引用数 (Scopus)

抄録

A 0.3-0.8 V low-power 2-bit/step asynchronous successive approximation register analog-to-digital converter (ADC) is presented. A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. Simple digital calibration is enabled by generating the reference internally. The prototype ADC fabricated in a 40 nm CMOS achieved a 44.3 dB signal-to-noise-plus-distortion ratio (SNDR) with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 4.8 fJ/conv-step at 0.4 V and operates down to 0.3 V.

本文言語English
論文番号6748934
ページ(範囲)356-368
ページ数13
ジャーナルIEEE Transactions on Very Large Scale Integration (VLSI) Systems
23
2
DOI
出版ステータスPublished - 2015 2月 1

ASJC Scopus subject areas

  • ソフトウェア
  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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