An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators

Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Shigeru Maya, Akihide Sai, Kohei Onizuka

研究成果: Article査読

14 被引用数 (Scopus)

抄録

A small-gate-count 8 bit bidirectional phase-domain MAC (PMAC) circuit is proposed to minimize both area and energy consumption of extremely energy-efficient deep neural network (DNN) accelerators, targeting the Internet-of-Things (IoT) edge devices operating with very strict power budgets (e.g., energy harvesting). PMAC consumes significantly less energy than standard fully digital MACs, due to its efficient analog accumulation nature based on gated-ring oscillator (GRO). The architectural analysis of energy-efficient accelerators is performed, and the energy budget analysis is disclosed. Furthermore, theoretical analysis of PMAC is conducted and comparisons with the conventional analog approaches are shown. By exploiting the DNN digital quantization noise, we further improve the PMAC energy efficiency by designing the internal gain. The bidirectional architecture proposed in this paper achieves an area comparable to those of digital MACs and up to a fivefold improvement in power efficiency. Moreover, the system design constraints are relaxed by eliminating the phase error originating in leakage currents. An asynchronous readout technique and a two-step digital-to-time converter (DTC) to enhance system throughput and compact implementation, respectively, are presented for the first time. We also present DNN hardware-software co-training procedures to show further scaling of the PMAC efficiency. Utilizing such techniques, the measured PMAC achieves peak efficiency of 12.4 TOPS/W in 28 nm CMOS.

本文言語English
論文番号8771205
ページ(範囲)2730-2742
ページ数13
ジャーナルIEEE Journal of Solid-State Circuits
54
10
DOI
出版ステータスPublished - 2019 10月
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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