An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.

本文言語English
ホスト出版物のタイトル2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
ページ31-32
ページ数2
DOI
出版ステータスPublished - 2014 3月 27
イベント2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore
継続期間: 2014 1月 202014 1月 23

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
国/地域Singapore
CitySuntec
Period14/1/2014/1/23

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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