An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

    研究成果: Conference contribution

    13 被引用数 (Scopus)

    抄録

    An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.

    本文言語English
    ホスト出版物のタイトル2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
    ページ381-384
    ページ数4
    DOI
    出版ステータスPublished - 2012 12 14
    イベント38th European Solid State Circuits Conference, ESSCIRC 2012 - Bordeaux, France
    継続期間: 2012 9 172012 9 21

    出版物シリーズ

    名前European Solid-State Circuits Conference
    ISSN(印刷版)1930-8833

    Other

    Other38th European Solid State Circuits Conference, ESSCIRC 2012
    CountryFrance
    CityBordeaux
    Period12/9/1712/9/21

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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