An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1μm DRAM

Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda

    研究成果: Conference contribution

    40 被引用数 (Scopus)

    抄録

    This paper presents an 8Tb/s 1pJ/b 0.8mm2/Tb/s quad data rate (QDR) inductive-coupling interface between 65nm CMOS GPU and 0.1μ m DRAM. The interface consists of 1024-bit parallel inductive-coupling transceivers operating at 8Gb/s/link. In the DRAM transceiver, data are multiplexed and demultiplexed by using a quadrature clock and XOR operation. This circuit technique for QDR compensates for transistor performance gap between the GPU and the DRAM to achieve 8Gb/s bandwidth. The clock for data retiming is recovered from the received data by using an injection-lock VCO. Clock links and clock distribution circuits are not needed, resulting in small layout area of 0.8mm2/Tb/s. Frontend of the transceiver is implemented using NMOS CML circuits with adaptive bias control. The transceiver's sensitivity to PVT variations is small, enabling all the 1024 parallel transceivers to operate at BER<10-16. It also reduces the design margin required of the transceiver, resulting in power reduction to 1pJ/b. Compared to the latest wired 40nm DRAM interface [1], the bandwidth is 32x higher, while the energy consumption is 1/8 and the layout area is 1/22.

    本文言語English
    ホスト出版物のタイトル2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
    ページ436-437
    ページ数2
    DOI
    出版ステータスPublished - 2010
    イベント2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States
    継続期間: 2010 2月 72010 2月 11

    出版物シリーズ

    名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
    53
    ISSN(印刷版)0193-6530

    Other

    Other2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
    国/地域United States
    CitySan Francisco, CA
    Period10/2/710/2/11

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

    フィンガープリント

    「An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1μm DRAM」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル