An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs

Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka

研究成果: Article査読


In this article, an active slew rate (SR) control IC for superjunction MOSFET (SJMOS) is proposed. Active gate control is an attractive technique to reduce switching (SW) losses by maintaining a constant drain voltage SR (<italic>dV</italic> <inline-formula> <tex-math notation="LaTeX">$_{d}$</tex-math> </inline-formula>/<italic>dt</italic>) of power devices. However, the conventional method for IGBT, GaN, and SiC devices cannot be applied to the active gate control of SJMOS because <italic>dV</italic> <inline-formula> <tex-math notation="LaTeX">$_{d}$</tex-math> </inline-formula>/<italic>dt</italic> is determined by the reverse recovery current (<inline-formula> <tex-math notation="LaTeX">$I_{\mathrm{RR}})$</tex-math> </inline-formula>, which is unique to SJMOS. In this article, a discrete-time feedback technique that can control <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm{RR}}$</tex-math> </inline-formula> generated before the drain voltage transition by reflecting the feedback result in the next SW is proposed. The <italic>dV</italic> <inline-formula> <tex-math notation="LaTeX">$_{d}$</tex-math> </inline-formula>/<italic>dt</italic> of SJMOS is kept constant by controlling <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm{RR}}$</tex-math> </inline-formula> with two resistors connected to the gate. In addition, the proposed technique can reduce the SW losses more than the control with one resistance value under the same <italic>dV</italic> <inline-formula> <tex-math notation="LaTeX">$_{d}$</tex-math> </inline-formula>/<italic>dt</italic> condition because the proposed technique can improve the rise time of the drain current without changing <italic>dV</italic> <inline-formula> <tex-math notation="LaTeX">$_{d}$</tex-math> </inline-formula>/<italic>dt</italic>. By using the proposed technique, <italic>dV</italic> <inline-formula> <tex-math notation="LaTeX">$_{d}$</tex-math> </inline-formula>/<italic>dt</italic> can be kept constant regardless of the load current, temperature, and threshold voltage of SJMOS. The proposed gate driver is implemented in 0.6-<inline-formula> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula>m CMOS, and the measured results show that <italic>dV</italic> <inline-formula> <tex-math notation="LaTeX">$_{d}$</tex-math> </inline-formula>/<italic>dt</italic> can be controlled to 3, 4.5, and 4.9 V/ns values, and the SW losses can be reduced by 25%. The turn-on delay reduction of 74% is also achieved by the proposed gate driver.

ジャーナルIEEE Journal of Solid-State Circuits
出版ステータスAccepted/In press - 2022

ASJC Scopus subject areas

  • 電子工学および電気工学


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