An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima

研究成果: Conference contribution

17 被引用数 (Scopus)

抄録

We propose a cryptographic accelerator for IPsec by using the NEC electronics' Dynamically Reconfigurable Processor (DRP). In our system, an embedded processor and DRP are integrated in a System-on-a-Chip (SoC) and multiple cryptographic tasks can be accelerated by DRP. Moreover, the virtual hardware mechanism, which dynamically changes its configuration data set, is introduced to realize more tasks on DRP. The evaluation results show that the throughput of each implemented cryptographic task outperformed a MIPS compatible embedded processor from 1.6 times to 7.8 times. In addition, it is shown that 80.7% of the run-time configuration overhead can be reduced by background configuration based on the double buffering method.

本文言語English
ホスト出版物のタイトルProceedings - 2005 IEEE International Conference on Field Programmable Technology
ページ163-170
ページ数8
DOI
出版ステータスPublished - 2005
イベント2005 IEEE International Conference on Field Programmable Technology - , Singapore
継続期間: 2005 12 112005 12 14

出版物シリーズ

名前Proceedings - 2005 IEEE International Conference on Field Programmable Technology
2005

Other

Other2005 IEEE International Conference on Field Programmable Technology
CountrySingapore
Period05/12/1105/12/14

ASJC Scopus subject areas

  • Engineering(all)

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