An adaptive Viterbi decoder on the dynamically reconfigurable processor

Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, Hideharu Amano

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics' DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the Signal to Noise Ratio. The power can be saved up to 58.3% and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long.

本文言語English
ホスト出版物のタイトルProceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006
ページ285-288
ページ数4
DOI
出版ステータスPublished - 2006 12 1
イベント2006 IEEE International Conference on Field Programmable Technology, FPT 2006 - Bangkok, Thailand
継続期間: 2006 12 132006 12 15

出版物シリーズ

名前Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

Other

Other2006 IEEE International Conference on Field Programmable Technology, FPT 2006
CountryThailand
CityBangkok
Period06/12/1306/12/15

ASJC Scopus subject areas

  • Software

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