An efficient and scalable implementation of sliding-window aggregate operator on FPGA

Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

This paper presents an efficient and scalable implementation of an FPGA-based accelerator for sliding-window aggregates over disordered data streams. With an increasing number of overlapping sliding-windows, the window aggregates have a serious scalability issue, especially when it comes to implementing them in parallel processing hardware (e.g., FPGAs). To address the issue, we propose a resource-efficient, scalable, and order-agnostic hardware design and its implementation by examining and integrating two key concepts, called Window-ID and Pane, which are originally proposed for software implementation, respectively. Evaluation results show that the proposed implementation scales well compared to the previous FPGA implementation in terms of both resource consumption and performance. The proposed design is fully pipelined and our implementation can process out-of-order data items, or tuples, at wire speed up to 200 million tuples per second.

本文言語English
ホスト出版物のタイトルProceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013
ページ112-121
ページ数10
DOI
出版ステータスPublished - 2013 12 1
外部発表はい
イベント2013 1st International Symposium on Computing and Networking, CANDAR 2013 - Matsuyama, Ehime, Japan
継続期間: 2013 12 42013 12 6

出版物シリーズ

名前Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013

Other

Other2013 1st International Symposium on Computing and Networking, CANDAR 2013
CountryJapan
CityMatsuyama, Ehime
Period13/12/413/12/6

ASJC Scopus subject areas

  • Computer Networks and Communications

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