An FPGA implementation of reconfigurable real-time vision architecture

A video processing architecture based on FPGA for real-time embedded vision systems is proposed in this paper. Recently, embedded vision systems are used in various applications. On the other hand, the throughput required to the system has been increasing as the high-definition vision replaces the current vision systems. Since more complex vision algorithms become available, higher performance and better expandability are requested accordingly. As a solution for this challenging situation, FPGA is now drawing more attention as an embedded vision system platform. In addition, high-level synthesis design is preferred instead of traditional low-level design based on hardware description languages with lower productivity. In this study, we implemented a video processing pipelined architecture which can offer flexibility for interchange processing modules. Each module was implemented using Verilog HDL and Vivado HLS for its evaluation.