An implementation methodology for Neural Network on a Low-end FPGA Board

Kaijie Wei, Koki Honda, Hideharu Amano

研究成果: Conference contribution

抄録

Artificial Intelligence(AI) has achieved unprecedented success in various fields including image/speech recognition which is useful for edge computing. Most of AI systems are implemented on power-hungry devices like GPU, high-end FPGA, or even TPU to process data with high performance. However, these energy budgets are often not affordable to edge computing. Low-end FPGA taking advantage of high energy-efficiency is a desirable platform to meet the requirements of image recognition working on small autonomous vehicles. In this paper, we propose the design methodology and implementation to adapt a neural network system to a low-end FPGA board using HLS description. The whole design consists of algorithm-level downscaling and hardware optimization. The former emphasizes the model downscale by considering accuracy. The latter applies various HLS design techniques to speed-up the application running on the target board. In the case study of tiny YOLO (You Only Look Once) v3, the model running on PYNQ-Z1 presents up to 22× acceleration comparing with the PYNQ ARM CPU. Energy efficiency also achieves 3× better than Xeon E5-2667.

本文言語English
ホスト出版物のタイトルProceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020
出版社Institute of Electrical and Electronics Engineers Inc.
ページ228-234
ページ数7
ISBN(電子版)9781728182216
DOI
出版ステータスPublished - 2020 11
イベント8th International Symposium on Computing and Networking, CANDAR 2020 - Virtual, Naha, Japan
継続期間: 2020 11 242020 11 27

出版物シリーズ

名前Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020

Conference

Conference8th International Symposium on Computing and Networking, CANDAR 2020
国/地域Japan
CityVirtual, Naha
Period20/11/2420/11/27

ASJC Scopus subject areas

  • 人工知能
  • 計算理論と計算数学
  • コンピュータ ネットワークおよび通信
  • コンピュータ サイエンスの応用
  • ソフトウェア

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