An inductive-coupling DC voltage transceiver for highly parallel wafer-level testing

Yoichi Yoshida; Koichi Nose; Yoshihiro Nakagawa; Koichiro Noguchi; Yasuhiro Morita; Masamoto Tago; Masayuki Mizuno; Tadahiro Kuroda

doi:10.1109/JSSC.2010.2061653

An inductive-coupling DC voltage transceiver for highly parallel wafer-level testing

Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda

研究成果: Article › 査読

10 被引用数 (Scopus)

抄録

A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 μm × 100 μm). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution.

本文言語	English
論文番号	5584951
ページ（範囲）	2057-2065
ページ数	9
ジャーナル	IEEE Journal of Solid-State Circuits
巻	45
号	10
DOI	https://doi.org/10.1109/JSSC.2010.2061653
出版ステータス	Published - 2010 10月

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/JSSC.2010.2061653

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引用スタイル

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AU - Tago, Masamoto

AU - Mizuno, Masayuki

AU - Kuroda, Tadahiro

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An inductive-coupling DC voltage transceiver for highly parallel wafer-level testing

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