An inductive-coupling DC voltage transceiver for highly parallel wafer-level testing

Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda

    研究成果: Article査読

    10 被引用数 (Scopus)

    抄録

    A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 μm × 100 μm). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution.

    本文言語English
    論文番号5584951
    ページ(範囲)2057-2065
    ページ数9
    ジャーナルIEEE Journal of Solid-State Circuits
    45
    10
    DOI
    出版ステータスPublished - 2010 10

    ASJC Scopus subject areas

    • 電子工学および電気工学

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