An On-Chip Ultra-Low-Power Hz-Range Ring Oscillator Based on Dynamic Leakage Suppression Logic

Jorge Canada, Yui Yoshida, Hiroki Miura, Nobuhiko Nakano

研究成果: Conference contribution

抄録

In this paper, simulation and experimental results of an ultra-low-power Hz-range ring oscillator are presented. The proposed circuit can operate from subthreshold voltage (0.24 V) to nominal voltage (1.8 V) and reaches power consumptions in the picowatt order. The design, based on Dynamic Leakage Suppression (DLS) logic, has been implemented in 0.18 um CMOS technology and uses sub-pF capacitors. Its main features are its low power consumption, small area, wide supply voltage range and utmost simplicity.

本文言語English
ホスト出版物のタイトルITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications
出版社Institute of Electrical and Electronics Engineers Inc.
ページ378-383
ページ数6
ISBN(電子版)9784885523281
出版ステータスPublished - 2020 7
イベント35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020 - Nagoya, Japan
継続期間: 2020 7 32020 7 6

出版物シリーズ

名前ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications

Conference

Conference35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020
CountryJapan
CityNagoya
Period20/7/320/7/6

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Information Systems and Management
  • Electrical and Electronic Engineering

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