An outside-rail opamp design targeting for future scaled transistors

Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai, Hiroki Ishikuro

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

An outside-rail output opamp targeting for future scaled MOSFETs is designed and the 3-V-output operation is successfully verified using 1.8-V standard CMOS process. This is the first experimental verification of an outside-rail opamp design which shows area advantage over un-scaled and insiderail design while keeping signal-to-noise ratio and gain bandwidth constant. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8V 0.18-μm standard CMOS process. The chip area is estimated to be 47% of the conventional opamp using a 0.35-μm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-mμ CMOS design due to reduced capacitor area.

本文言語English
ホスト出版物のタイトル2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
出版社IEEE Computer Society
ページ73-76
ページ数4
ISBN(印刷版)0780391624, 9780780391628
DOI
出版ステータスPublished - 2005
外部発表はい
イベント1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan, Province of China
継続期間: 2005 11月 12005 11月 3

出版物シリーズ

名前2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Other

Other1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
国/地域Taiwan, Province of China
CityHsinchu
Period05/11/105/11/3

ASJC Scopus subject areas

  • 電子工学および電気工学
  • 電子材料、光学材料、および磁性材料

フィンガープリント

「An outside-rail opamp design targeting for future scaled transistors」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル