An trace-driven performance prediction method for exploring noc design optimization

Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

研究成果: Conference contribution

抄録

The performance prediction for a NoC-based Chip Multi-Processor (CMP) is one of the main design concerns. Generally, there is a trade-off between accuracy and time overhead on the performance prediction of computer systems. In particular, the time overhead is proportional or exponential to the number of cores when using a cycle-accurate full-system simulation, such as gem5. In this study, we propose an accurate and scalable method to predict the influence of design NoC parameters on its performance. Our method counts the number of execution cycles when employing the target NoC based on the statistics of one-time execution of a full-system simulation using a fully-connected NoC. To evaluate the accuracy and execution time overhead, we use the case that randomly generates allocations of processors with 3D mesh topology NoC. Its Mean Absolute Percentage Error of the estimated cycles is about 4.7%, and the Maximum Absolute Percentage Error is about 8.5%.

本文言語English
ホスト出版物のタイトルProceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018
出版社Institute of Electrical and Electronics Engineers Inc.
ページ182-185
ページ数4
ISBN(電子版)9781538691847
DOI
出版ステータスPublished - 2018 12月 26
イベント6th International Symposium on Computing and Networking Workshops, CANDARW 2018 - Takayama, Japan
継続期間: 2018 11月 272018 11月 30

出版物シリーズ

名前Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018

Conference

Conference6th International Symposium on Computing and Networking Workshops, CANDARW 2018
国/地域Japan
CityTakayama
Period18/11/2718/11/30

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ
  • 統計学、確率および不確実性
  • コンピュータ サイエンスの応用

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