An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems

Peter Toth, Hiroki Ishikuro

研究成果: Conference contribution

抄録

This work presents a novel control loop concept to adjust dynamically a differential ring oscillators (DRO) biasing in order to improve the phase noise performance (PN) in the ultra-low-power domain. Applying this proposed feedback system on any DRO with a tail current source is possible. The following paper presents the proposed concept and includes measurements of a 180 nm CMOS integrated prototype system, which underlines the feasibility of the discussed idea. Measurements show an up to 35 dBc/Hz phase noise improvement with an active control loop. Moreover, the tuning range of the implemented ring oscillator is extended by about 430 % compared to fixed bias operation. These values are measured at a minimum oscillation power consumption of 55 pW/Hz. University LSI Design Contest ASP-DAC 2021

本文言語English
ホスト出版物のタイトルProceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
出版社Institute of Electrical and Electronics Engineers Inc.
ページ9-10
ページ数2
ISBN(電子版)9781450379991
DOI
出版ステータスPublished - 2021 1 18
イベント26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 - Virtual, Online, Japan
継続期間: 2021 1 182021 1 21

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
国/地域Japan
CityVirtual, Online
Period21/1/1821/1/21

ASJC Scopus subject areas

  • 電子工学および電気工学
  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計

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