Analysis and design of transceiver circuit and inductor layout for inductive inter-chip wireless superconnect

Noriyuki Miura, Daisuke Mizoguchi, Yusmeeraz Binti Yusof, Takayasu Sakurai, Tadahiro Kuroda

    研究成果: Paper査読

    21 被引用数 (Scopus)

    抄録

    A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by an equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communications distance, transmit power, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive Non-Return-to-Zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35μm CMOS. Accuracy of the models is verified. Bit error rate is investigated for various inductor layouts and communications distance. The maximum data rate is 1.25Gb/s/channel. Power dissipation is 43mW in the transmitter and 2.6mW in the receiver at 3.3V. If chip thickness is reduced to 30μm in 90nm device generation, power dissipation will be ImW/channel or bandwidth will be ITb/s/mm2.

    本文言語English
    ページ246-249
    ページ数4
    出版ステータスPublished - 2004 9 29
    イベント2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States
    継続期間: 2004 6 172004 6 19

    Other

    Other2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
    CountryUnited States
    CityHonolulu, HI
    Period04/6/1704/6/19

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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