A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the highfrequency performance of the rectifier block. Test chips are fabricated in a 0.18 μm CMOS process. With a pair of 700 × 700 μm2 on-chip inductors, the test chips achieve 10% peak efficiency and 36mW power transmission. Compared with the previous work the received power is 13 times larger for the same inductor size .
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