TY - GEN
T1 - Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench
AU - Sugimoto, Naru
AU - Miyajima, Takaaki
AU - Kuhara, Takuya
AU - Katuta, Yuki
AU - Mitsuichi, Takushi
AU - Amano, Hideharu
PY - 2013/12/1
Y1 - 2013/12/1
N2 - This paper presents a design of an FPGA-based Blokus Duo solver. It searches a game tree by using the miniMax algorithm with alpha-beta pruning and move ordering. In addition, HLS tool called CyberWorkBench (CWB) is used to implement hardware. By making the use of functions in CWB, parallel fully pipelined design is generated. The implemented solver works at 100MHz with Xilinx Spartan-6 XC6SLX45 FPGA on the Digilent Atlys board. It can search states after three moves in most cases.
AB - This paper presents a design of an FPGA-based Blokus Duo solver. It searches a game tree by using the miniMax algorithm with alpha-beta pruning and move ordering. In addition, HLS tool called CyberWorkBench (CWB) is used to implement hardware. By making the use of functions in CWB, parallel fully pipelined design is generated. The implemented solver works at 100MHz with Xilinx Spartan-6 XC6SLX45 FPGA on the Digilent Atlys board. It can search states after three moves in most cases.
UR - http://www.scopus.com/inward/record.url?scp=84894185942&partnerID=8YFLogxK
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U2 - 10.1109/FPT.2013.6718427
DO - 10.1109/FPT.2013.6718427
M3 - Conference contribution
AN - SCOPUS:84894185942
SN - 9781479921990
T3 - FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology
SP - 498
EP - 501
BT - FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology
T2 - 2013 12th International Conference on Field-Programmable Technology, FPT 2013
Y2 - 9 December 2013 through 11 December 2013
ER -