Attempt-1: A reconfigurable multiprocessor testbed

Keisuke Inoue, Tohru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

The future advanced technologies of devices will enable to implement some number of processors into a single chip. We call such a chip the multiprocessor-chip. In such a multiprocessor-chip, architectural trade-off is completely different from current bus connected multiprocessors. In order to emulate such future multiprocessors, a reconfigurable testbed multiprocessor ATTEMPT-1 is proposed. By using programmable devices (CPLDs and FPGAs) in the core of the system, various parameters of the cache and bus system are selectable. Since the each core of controller is described in the HDL (Hardware Description Language) and implemented on CPLD, cache protocols and bus protocols can be changed just by rewriting description on the state transitions. By using high speed FPGAs in the data path, enough high speed (25MHz clock) is kept in spite of its flexibilty.

本文言語English
ホスト出版物のタイトルField-Programmable Logic
ホスト出版物のサブタイトルSmart Applications, New Paradigms and Compilers - 6th International Workshop on Field-Programmable Logic and Applications, FPL 1996, Proceedings
編集者Reiner W. Hartenstein, Manfred Glesner
出版社Springer Verlag
ページ200-209
ページ数10
ISBN(印刷版)9783540617303
DOI
出版ステータスPublished - 1996
イベント6th International Workshop on Field-Programmable Logic and Applications, FPL 1996 - Darmstadt, Germany
継続期間: 1996 9 231996 9 25

出版物シリーズ

名前Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
1142
ISSN(印刷版)0302-9743
ISSN(電子版)1611-3349

Other

Other6th International Workshop on Field-Programmable Logic and Applications, FPL 1996
CountryGermany
CityDarmstadt
Period96/9/2396/9/25

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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