AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

研究成果: Conference contribution

24 被引用数 (Scopus)

抄録

Various parallel applications, such as numerical convergent computation and multimedia processing, have intrinsic tolerance to inaccuracies that allow soft errors, i.e. bit flips, on a chip. However, existing Network-on-Chips (NoCs) guarantee error-free data transfer; thus, encountering limits to reduce the power consumption. In this context, we propose an approximate dual-voltage NoC, called AxNoC. An AxNoC router uses a per-flit look-ahead power management so that headers and important-data flits are perfectly transferred at a high voltage while the remaining flits may incur bit flips by decreasing the supply voltage. An AxNoC router isolates the critical path when the supply voltage is low since such a critical path is enabled only at high voltage. The critical path isolation enables low-voltage operation to work at the same operating frequency at high voltage. An AxNoC router was implemented using a 28nm process and the evaluation results illustrate its efficiency to reduce the power consumption reaching up to 43% while incurring a small area overhead that does not exceed 6.2%. We also demonstrate that AxNoC exhibits an acceptable accuracy illustrated in a sufficiently small geomean of error.

本文言語English
ホスト出版物のタイトル2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781538648933
DOI
出版ステータスPublished - 2018 10月 26
イベント12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018 - Torino, Italy
継続期間: 2018 10月 42018 10月 5

出版物シリーズ

名前2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018

Other

Other12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018
国/地域Italy
CityTorino
Period18/10/418/10/5

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ

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