BIPOLAR GBIT/S 8 multiplied by 8 BIT S/P, P/S CONVERTER LSI.

Michihiro Hirata, Masao Suzuki, Naoaki Yamanaka, Yousuke Yamamoto

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

A Si bipolar very high-speed 8-channel multiplied by 8-bit Serial/Parallel and Parallel/Serial conversion LSI (SPPS-LSI), having 1. 5 Gb/s throughput is developed for high-speed digital communication systems. To achieve high performance, a novel data conversion method is adopted. By applying a sophisticated circuit design and SST-1A process technology, a high-speed and low-power LSI is achieved with small chip size.

本文言語English
ホスト出版物のタイトルConference on Solid State Devices and Materials
出版社Business Cent for Academic Soc Japan
ページ271-274
ページ数4
ISBN(印刷版)493081314X
出版ステータスPublished - 1986 12 1
外部発表はい

出版物シリーズ

名前Conference on Solid State Devices and Materials

ASJC Scopus subject areas

  • 工学(全般)

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