Bit-line leakage compensation scheme for low-voltage SRAM's

Ken'ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda

研究成果: Paper査読

9 被引用数 (Scopus)

抄録

The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low Vth and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. Vth can be lowered to 0.23 VDD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V VDD compared with the case where this scheme is not applied.

本文言語English
ページ70-71
ページ数2
出版ステータスPublished - 2000
外部発表はい
イベント2000 Symposium on VLSI Circuits - Honolulu, HI, USA
継続期間: 2000 6月 152000 6月 17

Other

Other2000 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period00/6/1500/6/17

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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