BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Kota Ando; Kodai Ueyoshi; Kentaro Orimo; Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Tadahiro Kuroda; Masato Motomura

doi:10.1109/JSSC.2017.2778702

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

研究成果: Article › 査読

68 被引用数 (Scopus)

抄録

A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.

本文言語	English
ページ（範囲）	983-994
ページ数	12
ジャーナル	IEEE Journal of Solid-State Circuits
巻	53
号	4
DOI	https://doi.org/10.1109/JSSC.2017.2778702
出版ステータス	Published - 2018 4月

ASJC Scopus subject areas

電子工学および電気工学

UN SDG

この成果は、次の持続可能な開発目標に貢献しています

文献へのアクセス

10.1109/JSSC.2017.2778702

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引用スタイル

Ando, K., Ueyoshi, K., Orimo, K., Yonekawa, H., Sato, S., Nakahara, H., Takamaeda-Yamazaki, S., Ikebe, M., Asai, T., Kuroda, T., & Motomura, M. (2018). BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE Journal of Solid-State Circuits, 53(4), 983-994. https://doi.org/10.1109/JSSC.2017.2778702

BRein Memory : A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. / Ando, Kota; Ueyoshi, Kodai; Orimo, Kentaro; Yonekawa, Haruyoshi; Sato, Shimpei; Nakahara, Hiroki; Takamaeda-Yamazaki, Shinya; Ikebe, Masayuki; Asai, Tetsuya; Kuroda, Tadahiro; Motomura, Masato.

In: IEEE Journal of Solid-State Circuits, Vol. 53, No. 4, 04.2018, p. 983-994.

研究成果: Article › 査読

Ando, K, Ueyoshi, K, Orimo, K, Yonekawa, H, Sato, S, Nakahara, H, Takamaeda-Yamazaki, S, Ikebe, M, Asai, T, Kuroda, T & Motomura, M 2018, 'BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W', IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 983-994. https://doi.org/10.1109/JSSC.2017.2778702

Ando, Kota ; Ueyoshi, Kodai ; Orimo, Kentaro ; Yonekawa, Haruyoshi ; Sato, Shimpei ; Nakahara, Hiroki ; Takamaeda-Yamazaki, Shinya ; Ikebe, Masayuki ; Asai, Tetsuya ; Kuroda, Tadahiro ; Motomura, Masato. / BRein Memory : A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. In: IEEE Journal of Solid-State Circuits. 2018 ; Vol. 53, No. 4. pp. 983-994.

@article{9e5be92965704ef687d044d0d091a613,

title = "BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W",

abstract = "A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.",

keywords = "Binary neural networks, in-memory processing, near-memory processing, neural networks, reconfigurable array, ternary neural networks",

author = "Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura",

note = "Funding Information: Manuscript received August 3, 2017; revised October 16, 2017; accepted November 17, 2017. Date of publication December 19, 2017; date of current version March 23, 2018. This paper was approved by Guest Editor Makoto Ikeda. This work was supported by JST ACCEL, Japan, under Grant JPM-JAC1502. (Corresponding author: Kota Ando.) K. Ando, K. Ueyoshi, K. Orimo, S. Takamaeda-Yamazaki, M. Ikebe, T. Asai, and M. Motomura are with the Graduate School of Information Science and Technology, Hokkaido University, Sapporo 060-0814, Japan (e-mail: ando@lalsie.ist.hokudai.ac.jp). Publisher Copyright: {\textcopyright} 2012 IEEE.",

year = "2018",

month = apr,

doi = "10.1109/JSSC.2017.2778702",

language = "English",

volume = "53",

pages = "983--994",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - BRein Memory

T2 - A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

AU - Ando, Kota

AU - Ueyoshi, Kodai

AU - Orimo, Kentaro

AU - Yonekawa, Haruyoshi

AU - Sato, Shimpei

AU - Nakahara, Hiroki

AU - Takamaeda-Yamazaki, Shinya

AU - Ikebe, Masayuki

AU - Asai, Tetsuya

AU - Kuroda, Tadahiro

AU - Motomura, Masato

N1 - Funding Information: Manuscript received August 3, 2017; revised October 16, 2017; accepted November 17, 2017. Date of publication December 19, 2017; date of current version March 23, 2018. This paper was approved by Guest Editor Makoto Ikeda. This work was supported by JST ACCEL, Japan, under Grant JPM-JAC1502. (Corresponding author: Kota Ando.) K. Ando, K. Ueyoshi, K. Orimo, S. Takamaeda-Yamazaki, M. Ikebe, T. Asai, and M. Motomura are with the Graduate School of Information Science and Technology, Hokkaido University, Sapporo 060-0814, Japan (e-mail: ando@lalsie.ist.hokudai.ac.jp). Publisher Copyright: © 2012 IEEE.

PY - 2018/4

Y1 - 2018/4

N2 - A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.

AB - A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.

KW - Binary neural networks

KW - in-memory processing

KW - near-memory processing

KW - neural networks

KW - reconfigurable array

KW - ternary neural networks

UR - http://www.scopus.com/inward/record.url?scp=85039791875&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85039791875&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2017.2778702

DO - 10.1109/JSSC.2017.2778702

M3 - Article

AN - SCOPUS:85039791875

VL - 53

SP - 983

EP - 994

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 4

ER -