TY - JOUR
T1 - BRein Memory
T2 - A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W
AU - Ando, Kota
AU - Ueyoshi, Kodai
AU - Orimo, Kentaro
AU - Yonekawa, Haruyoshi
AU - Sato, Shimpei
AU - Nakahara, Hiroki
AU - Takamaeda-Yamazaki, Shinya
AU - Ikebe, Masayuki
AU - Asai, Tetsuya
AU - Kuroda, Tadahiro
AU - Motomura, Masato
N1 - Funding Information:
Manuscript received August 3, 2017; revised October 16, 2017; accepted November 17, 2017. Date of publication December 19, 2017; date of current version March 23, 2018. This paper was approved by Guest Editor Makoto Ikeda. This work was supported by JST ACCEL, Japan, under Grant JPM-JAC1502. (Corresponding author: Kota Ando.) K. Ando, K. Ueyoshi, K. Orimo, S. Takamaeda-Yamazaki, M. Ikebe, T. Asai, and M. Motomura are with the Graduate School of Information Science and Technology, Hokkaido University, Sapporo 060-0814, Japan (e-mail: ando@lalsie.ist.hokudai.ac.jp).
Publisher Copyright:
© 2012 IEEE.
PY - 2018/4
Y1 - 2018/4
N2 - A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.
AB - A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.
KW - Binary neural networks
KW - in-memory processing
KW - near-memory processing
KW - neural networks
KW - reconfigurable array
KW - ternary neural networks
UR - http://www.scopus.com/inward/record.url?scp=85039791875&partnerID=8YFLogxK
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U2 - 10.1109/JSSC.2017.2778702
DO - 10.1109/JSSC.2017.2778702
M3 - Article
AN - SCOPUS:85039791875
VL - 53
SP - 983
EP - 994
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 4
ER -