C4: An FPGA-based compression algorithm for expether

Hideki Shimura, Hiroyuki Noda, Hideharu Amano

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

PCI Express (PCIe) has been widely used as an I/O bus connecting CPU and GPUs. In order to resolve the limitation of the number of PCIe ports, NEC Corporation developed ExpEther for expanding PCIe to Ethernet. Since Ethernet often becomes a bottleneck of communication, a conventional research proposed to implement a compression/decompression mechanism by using existing data compression mechanisms to reduce the size of data transferring on Ethernet. However, data compression mechanisms used in the research were only efficient for a limited input data pattern. In this paper, we proposed a novel data compression algorithm called C4, and implemented it on Xilinx Virtex-7 FPGA as an experimental environment of ExpEther. As a result, the proposed method can reduce the transfer time by 52.5%, superior to 49.7% with the conventional method. According to the evaluation of the hardware resource utilization rate, we showed that the proposed algorithm can be implemented in the FPGA used in the ExpEther NIC.

本文言語English
ホスト出版物のタイトルProceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018
出版社Institute of Electrical and Electronics Engineers Inc.
ページ356-362
ページ数7
ISBN(電子版)9781538691847
DOI
出版ステータスPublished - 2018 12月 26
イベント6th International Symposium on Computing and Networking Workshops, CANDARW 2018 - Takayama, Japan
継続期間: 2018 11月 272018 11月 30

出版物シリーズ

名前Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018

Conference

Conference6th International Symposium on Computing and Networking Workshops, CANDARW 2018
国/地域Japan
CityTakayama
Period18/11/2718/11/30

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ
  • 統計学、確率および不確実性
  • コンピュータ サイエンスの応用

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