Cache coherency protocol for multiprocessor chip

Takuya Terasawa, Satoshi Ogura, Keisuke Inoue, Hideharu Amano

研究成果: Conference article

5 引用 (Scopus)

抜粋

A snoop cache protocol is proposed for the WSI implementation which minimizes the access to the shared memory. In modified-Keio protocol, both write-invalidate and write-update type protocols can be used according to the nature of the shared data. It also supports the simple synchronization mechanism with Fetch&Dec operation and inter-processor interrupt. Detailed simulation with practical parallel applications demonstrates the efficiency of this proposed protocol.

元の言語English
ページ(範囲)238-247
ページ数10
ジャーナルProceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
出版物ステータスPublished - 1995 1 1
外部発表Yes
イベントProceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
継続期間: 1995 1 181995 1 20

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Condensed Matter Physics

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