Cache line impact on 3D PDE solvers

Masaaki Kondo, Mitsugu Iwamoto, Hiroshi Nakamura

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Because performance disparity between processor and main memory is serious, it is necessary to reduce off-chip memory accesses by exploiting temporal locality. Loop tiling is a well-known optimization which enhances data locality. In this paper, we show a new cost model to select the best tile size in 3D partial differential equations. Our cost model carefully takes account of the effect of cache line. We present performance evaluation of our cost models. The evaluation results reveal the superiority of our cost model to other cost models proposed so far.

本文言語English
ホスト出版物のタイトルHigh Performance Computing - 4th International Symposium, ISHPC 2002, Proceedings
ページ301-309
ページ数9
DOI
出版ステータスPublished - 2002
外部発表はい
イベント4th International Symposium on High Performance Computing, ISHPC 2002 - Kansai Science City, Japan
継続期間: 2002 5月 152002 5月 17

出版物シリーズ

名前Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2327 LNCS
ISSN(印刷版)0302-9743
ISSN(電子版)1611-3349

Conference

Conference4th International Symposium on High Performance Computing, ISHPC 2002
国/地域Japan
CityKansai Science City
Period02/5/1502/5/17

ASJC Scopus subject areas

  • 理論的コンピュータサイエンス
  • コンピュータ サイエンス(全般)

フィンガープリント

「Cache line impact on 3D PDE solvers」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル