TY - GEN
T1 - Cache line impact on 3D PDE solvers
AU - Kondo, Masaaki
AU - Iwamoto, Mitsugu
AU - Nakamura, Hiroshi
PY - 2002
Y1 - 2002
N2 - Because performance disparity between processor and main memory is serious, it is necessary to reduce off-chip memory accesses by exploiting temporal locality. Loop tiling is a well-known optimization which enhances data locality. In this paper, we show a new cost model to select the best tile size in 3D partial differential equations. Our cost model carefully takes account of the effect of cache line. We present performance evaluation of our cost models. The evaluation results reveal the superiority of our cost model to other cost models proposed so far.
AB - Because performance disparity between processor and main memory is serious, it is necessary to reduce off-chip memory accesses by exploiting temporal locality. Loop tiling is a well-known optimization which enhances data locality. In this paper, we show a new cost model to select the best tile size in 3D partial differential equations. Our cost model carefully takes account of the effect of cache line. We present performance evaluation of our cost models. The evaluation results reveal the superiority of our cost model to other cost models proposed so far.
UR - http://www.scopus.com/inward/record.url?scp=45649083268&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=45649083268&partnerID=8YFLogxK
U2 - 10.1007/3-540-47847-7_26
DO - 10.1007/3-540-47847-7_26
M3 - Conference contribution
AN - SCOPUS:45649083268
SN - 354043674X
SN - 9783540436744
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 301
EP - 309
BT - High Performance Computing - 4th International Symposium, ISHPC 2002, Proceedings
T2 - 4th International Symposium on High Performance Computing, ISHPC 2002
Y2 - 15 May 2002 through 17 May 2002
ER -