TY - GEN
T1 - Comparative performance analysis of dual-rail domino logic and CMOS logic under near-threshold operation
AU - Maruyama, Tsuyoshi
AU - Hamada, Mototsugu
AU - Kuroda, Tadahiro
N1 - Funding Information:
This work was supported by JST ACCEL Grant Number JPMJAC1502, Japan.
PY - 2019/1/22
Y1 - 2019/1/22
N2 - The designs of an asynchronous dual-rail domino logic (DRDL) and the conventional CMOS logic under near-threshold operation are compared. The delay time and energy consumption of an 8-bit full adder pipeline are simulated using HSPICE with 180-nm CMOS technology. The results show that, considering process variations, DRDL is faster than CMOS below 1.1 V. The delay performance of DRDL at 0.25 V is equivalent to that of CMOS at 0.4 V, while the energy-delay product of DRDL is 40% smaller than that of CMOS.
AB - The designs of an asynchronous dual-rail domino logic (DRDL) and the conventional CMOS logic under near-threshold operation are compared. The delay time and energy consumption of an 8-bit full adder pipeline are simulated using HSPICE with 180-nm CMOS technology. The results show that, considering process variations, DRDL is faster than CMOS below 1.1 V. The delay performance of DRDL at 0.25 V is equivalent to that of CMOS at 0.4 V, while the energy-delay product of DRDL is 40% smaller than that of CMOS.
KW - Asynchronous circuit
KW - Dual-rail domino logic
KW - Energy-delay product
KW - Full adder
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U2 - 10.1109/MWSCAS.2018.8624078
DO - 10.1109/MWSCAS.2018.8624078
M3 - Conference contribution
AN - SCOPUS:85062207525
T3 - Midwest Symposium on Circuits and Systems
SP - 25
EP - 28
BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Y2 - 5 August 2018 through 8 August 2018
ER -