抄録
The designs of an asynchronous dual-rail domino logic (DRDL) and the conventional CMOS logic under near-threshold operation are compared. The delay time and energy consumption of an 8-bit full adder pipeline are simulated using HSPICE with 180-nm CMOS technology. The results show that, considering process variations, DRDL is faster than CMOS below 1.1 V. The delay performance of DRDL at 0.25 V is equivalent to that of CMOS at 0.4 V, while the energy-delay product of DRDL is 40% smaller than that of CMOS.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018 |
| 出版者 | Institute of Electrical and Electronics Engineers Inc. |
| ページ | 25-28 |
| ページ数 | 4 |
| ISBN（電子版） | 9781538673928 |
| DOI | |
| 出版物ステータス | Published - 2019 1 22 |
| イベント | 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada 継続期間: 2018 8 5 → 2018 8 8 |
出版物シリーズ
| 名前 | Midwest Symposium on Circuits and Systems |
|---|---|
| 巻 | 2018-August |
| ISSN（印刷物） | 1548-3746 |
Conference
| Conference | 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 |
|---|---|
| 国 | Canada |
| 市 | Windsor |
| 期間 | 18/8/5 → 18/8/8 |
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ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
これを引用
Comparative performance analysis of dual-rail domino logic and CMOS logic under near-threshold operation. / Maruyama, Tsuyoshi; Hamada, Mototsugu; Kuroda, Tadahiro.
2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 25-28 8624078 (Midwest Symposium on Circuits and Systems; 巻 2018-August).研究成果: Conference contribution
}
TY - GEN
T1 - Comparative performance analysis of dual-rail domino logic and CMOS logic under near-threshold operation
AU - Maruyama, Tsuyoshi
AU - Hamada, Mototsugu
AU - Kuroda, Tadahiro
PY - 2019/1/22
Y1 - 2019/1/22
N2 - The designs of an asynchronous dual-rail domino logic (DRDL) and the conventional CMOS logic under near-threshold operation are compared. The delay time and energy consumption of an 8-bit full adder pipeline are simulated using HSPICE with 180-nm CMOS technology. The results show that, considering process variations, DRDL is faster than CMOS below 1.1 V. The delay performance of DRDL at 0.25 V is equivalent to that of CMOS at 0.4 V, while the energy-delay product of DRDL is 40% smaller than that of CMOS.
AB - The designs of an asynchronous dual-rail domino logic (DRDL) and the conventional CMOS logic under near-threshold operation are compared. The delay time and energy consumption of an 8-bit full adder pipeline are simulated using HSPICE with 180-nm CMOS technology. The results show that, considering process variations, DRDL is faster than CMOS below 1.1 V. The delay performance of DRDL at 0.25 V is equivalent to that of CMOS at 0.4 V, while the energy-delay product of DRDL is 40% smaller than that of CMOS.
KW - Asynchronous circuit
KW - Dual-rail domino logic
KW - Energy-delay product
KW - Full adder
UR - http://www.scopus.com/inward/record.url?scp=85062207525&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85062207525&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2018.8624078
DO - 10.1109/MWSCAS.2018.8624078
M3 - Conference contribution
AN - SCOPUS:85062207525
T3 - Midwest Symposium on Circuits and Systems
SP - 25
EP - 28
BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -