Comparative performance analysis of dual-rail domino logic and CMOS logic under near-threshold operation

Tsuyoshi Maruyama, Mototsugu Hamada, Tadahiro Kuroda

    研究成果: Conference contribution

    抄録

    The designs of an asynchronous dual-rail domino logic (DRDL) and the conventional CMOS logic under near-threshold operation are compared. The delay time and energy consumption of an 8-bit full adder pipeline are simulated using HSPICE with 180-nm CMOS technology. The results show that, considering process variations, DRDL is faster than CMOS below 1.1 V. The delay performance of DRDL at 0.25 V is equivalent to that of CMOS at 0.4 V, while the energy-delay product of DRDL is 40% smaller than that of CMOS.

    本文言語English
    ホスト出版物のタイトル2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
    出版社Institute of Electrical and Electronics Engineers Inc.
    ページ25-28
    ページ数4
    ISBN(電子版)9781538673928
    DOI
    出版ステータスPublished - 2019 1 22
    イベント61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada
    継続期間: 2018 8 52018 8 8

    出版物シリーズ

    名前Midwest Symposium on Circuits and Systems
    2018-August
    ISSN(印刷版)1548-3746

    Conference

    Conference61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
    国/地域Canada
    CityWindsor
    Period18/8/518/8/8

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

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