Data movement optimization for software-controlled on-chip memory

Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In order to overcome performance degradation caused by performance disparity between processor and main memory, there have been proposed several new VLSI architectures which have software controlled on-chip memory in addition to the conventional cache. However, users must specify data allocation/replacement on software controlled on-chip memory and data transfer between the on-chip and off-chip memories to achieve higher performance by utilizing on-chip memory. Because such properties are automatically controlled by hardware in conventional caches, a cost of optimization for a program becomes a matter that should be considered. In this paper, we propose an data movement optimization technique for software-controlled on-chip memory. We evaluated the proposed method using two applications. The results reveal that the proposed technique can drastically reduce memory stall cycles and achieve high performance.

本文言語English
ホスト出版物のタイトルProceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004
ページ120-127
ページ数8
DOI
出版ステータスPublished - 2004
外部発表はい
イベントProceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004 - Madrid, Spain
継続期間: 2004 2 152004 2 15

出版物シリーズ

名前Proceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004

Conference

ConferenceProceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004
国/地域Spain
CityMadrid
Period04/2/1504/2/15

ASJC Scopus subject areas

  • 工学(全般)

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