Design and implementation fine-grained power gating on microprocessor functional units

Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano

研究成果: Article査読

3 被引用数 (Scopus)

抄録

In this paper, we present a prototype MIPS R3000 processor, which integrates the fine-grained power gating technique into its functional units. To reduce the leakage power consumption, functional units, such as multiplier and divider can be power-gated individually according to the workload of the execution program. The prototype chip . Geyser-1 has been implemented with Fujitsu's 65 nm CMOS technology; and to facilitate the design process with fine-grained power gating, a fully automated design flow has also been proposed. Comprehensive real-chip evaluations have been performed to verify the leakage reduction efficiency. According the evaluation results with benchmark programs, the fine-grained power gating can reduce the power of the processor by 5% at 25°C and 23% at 80°C.

本文言語English
ページ(範囲)182-192
ページ数11
ジャーナルIPSJ Transactions on System LSI Design Methodology
4
DOI
出版ステータスPublished - 2011

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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