Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor

研究成果: Conference contribution

6 引用 (Scopus)

抜粋

Viterbi decoder implemented with hard-wired logic often requires extra cost and consuming power by using individual logic for various constraint length and decode precisions. Although the redundant hardware which is not used in the given condition can be omitted by replacing the hard-wired logic on FPGA, the time for loading configuration data often takes milliseconds and causes too long system stall. In this paper, we implemented the Viterbi algorithms whose constraint length are from 3 to 5 on coarse grained dynamically reconfigurable processor DAPDNA-II and replaced them according to the requirement. A certain thresh-old of BER is set for a fixed SNR and the Viterbi decoder with multiple constraint lengths is simulated. In the result of evaluation, when at least 4.50 Mbps throughput is ensured even with frequent reconfiguration was performed, the power consumption is reduced by 30% - 80% compared with the case when a constraint length of the best performance is utilized.

元の言語English
ホスト出版物のタイトルProceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008
ページ247-252
ページ数6
DOI
出版物ステータスPublished - 2008 12 1
イベント2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008 - Cancun, Mexico
継続期間: 2008 12 32008 12 5

出版物シリーズ

名前Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008

Other

Other2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008
Mexico
Cancun
期間08/12/308/12/5

    フィンガープリント

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

これを引用

Kishimoto, Y., Haruyama, S., & Amano, H. (2008). Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor. : Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008 (pp. 247-252). [4731802] (Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008). https://doi.org/10.1109/ReConFig.2008.39