Design and implementation of on-chip adaptive router with predictor for regional congestion

Masakazu Taniguchi, Hiroki Matsutani, Nobuyuki Yamasaki

研究成果: Conference contribution

3 引用 (Scopus)

抜粋

Many-core processor is one of attractive solutions to Cyber-Physical Systems (CPS) that demands high computational power since it can enclose many computational elements into a single physical chip. Network-on-Chip (NoC) that connects the processing cores is the key in terms of the cost, performance, and power in such systems. Although NoCs typically employ simple deterministic routing algorithms in order to reduce the complexity of on-chip routers, such deterministic algorithms do not avoid traffic congestion and thus the network throughput is degraded when the traffic pattern has localities. On the other hand, complex algorithms require large hardware cost and will be a problem for CPS whose hardware cost is limited. In this paper, we propose an adaptive on-chip router with Predictor for Regional Congestion (PRC) in order to improve the network throughput with modest hardware overhead. The proposed PRC routers exchange their past and predicted future congestion information with each other. Then, each router synthesizes its regional congestion information based on the local and received information in order to route packets without congestion. The simulation results show that the proposed routers improve the average throughput by 17.2% compared to a congestion-aware router that employes local information only. The RTL design of the proposed router shows that the area overhead is only 2.6% and additional wiring requirement for each router port is only three.

元の言語English
ホスト出版物のタイトルProceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011
ページ22-27
ページ数6
DOI
出版物ステータスPublished - 2011 12 1
イベント1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011 - Toyama, Japan
継続期間: 2011 8 282011 8 31

出版物シリーズ

名前Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011
2

Other

Other1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
Japan
Toyama
期間11/8/2811/8/31

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Networks and Communications

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  • これを引用

    Taniguchi, M., Matsutani, H., & Yamasaki, N. (2011). Design and implementation of on-chip adaptive router with predictor for regional congestion. : Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011 (pp. 22-27). [602904] (Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011; 巻数 2). https://doi.org/10.1109/RTCSA.2011.61