Design automation methodology of a critical path monitor for adaptive voltage controls

Ryosuke Kazami, Hayate Okuhara, Hideharu Amano

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

The development of recent CMOS technologies such as Fully Depleted Silicon on Insulator (FD-SOI) allows VLSI systems to operate with lower power than the conventional bulk transistors [1, 2]. Thanks to its high degree of noise immunity, low power supply voltages (VDD) can be applied to the FD-SOI devices. Also, since the effect of body biasing is further endorsed in such devices, adaptive voltage control for both power supply voltage and body bias voltages (VBN for nMOS and VBP for pMOS) can be aggressively used.

本文言語English
ホスト出版物のタイトル21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ページ1-3
ページ数3
ISBN(電子版)9781538661024
DOI
出版ステータスPublished - 2018 6 5
イベント21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Yokohama, Japan
継続期間: 2018 4 182018 4 20

出版物シリーズ

名前21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings

Other

Other21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018
国/地域Japan
CityYokohama
Period18/4/1818/4/20

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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