Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays

Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tanbunheng, Takuro Nakamura, Takashi Nishimura, Hideharu Amano

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameterized. By specifying architectural parameters, it can automatically generate RTL model, simulation environment, and finally chip layout. In our DRPA generator, although the fundamental design of a processing element (PE) and an inter-PE connection is fixed, the array size, PE granularity, and connection flexibilities of intra/inter PE are selectable. In this paper, we have generated various types of DRPAs and evaluated semiconductor area and speed by using the AS-PLA/STARC 90-nm CMOS technology. From evaluation results, fundamental trade-offs between architectural parameters and area/delay are analyzed.

本文言語English
ホスト出版物のタイトルProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
ページ796-799
ページ数4
DOI
出版ステータスPublished - 2007
イベント2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands
継続期間: 2007 8月 272007 8月 29

出版物シリーズ

名前Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2007 International Conference on Field Programmable Logic and Applications, FPL
国/地域Netherlands
CityAmsterdam
Period07/8/2707/8/29

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学

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