Design of a low power NoC router using marching memory through type

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

Power consumption of Network-on-Chip (NoC) is becoming more important in many core processors. Input buffers utilized in routers consume a significant part of the total power of NoCs. In order to reduce this power consumption, a novel power efficient memory called Marching Memory Through type (MMTH) is introduced. By connecting transparent latches in tandem, MMTH achieves high speed operation with a low power consumption. MMTH, however, requires a certain overhead at read operation, and hence we propose a latency reduction scheme based on the look-ahead routing. The proposed router was designed in Renesas's 40nm process and compared with a standard router using conventional register-based FIFOs in terms of the network performance, application performance, and power consumption. The result of evaluation shows that the proposed router reduces the power consumption by 42.4% on average at 2GHz and the expense of only 0.5-2.0% performance overhead.

本文言語English
ホスト出版物のタイトルProceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014
編集者Davide Bertozzi, Luca Benini, Sudhakar Yalamanchili, Joerg Henkel
出版社Institute of Electrical and Electronics Engineers Inc.
ページ111-118
ページ数8
ISBN(電子版)9781479953479
DOI
出版ステータスPublished - 2015 1 13
イベント8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014 - Ferrara, Italy
継続期間: 2014 9 172014 9 19

出版物シリーズ

名前Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014

Other

Other8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014
国/地域Italy
CityFerrara
Period14/9/1714/9/19

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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