Design of new logic architectures utilizing optimized suspended-gate single-electron transistors

Benjamin Pruvost, Ken Uchida, Hiroshi Mizuta, Shunri Oda

研究成果: Article査読

1 被引用数 (Scopus)

抄録

The operation and performances of the suspended-gate single-electron transistor (SET) are investigated through simulation. The movable gate is 3-D optimized, so that low actuation voltage (0.4 V), fast switching (1 ns), and ultralow pull-in energy (0.015 fJ) are simulated. A two-state capacitor model based on the 3-D results is then embedded with a SET analytical model in a SPICE environment to investigate the operation of the device. Through the control of the Coulomb oscillation characteristics, the position of the movable gate enables a background charge insensitive coding of the information. New circuit architectures with applications in cellular nonlinear network and pattern matching are also proposed and simulated.

本文言語English
論文番号5223702
ページ(範囲)504-512
ページ数9
ジャーナルIEEE Transactions on Nanotechnology
9
4
DOI
出版ステータスPublished - 2010 7月
外部発表はい

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学

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