Design of resource sharing reconfigurable ΔΣ SAR-ADC

Motomi Ishizuka, Kohei Yamada, Hiroki Ishikuro

    研究成果: Conference contribution

    抄録

    This paper presents an ADC with re-configurability between SAR-only mode and delta-sigma (ΔΣ assisted mode). The ΔΣ assisted mode brings resolution enhancement. Proposed ADC shares a capacitor array for SAR, feedback DAC, and integrator capacitor in ΔΣ loop, which can reduce the circuit size. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at 32 MS/s and power consumption of 0.55 mW. The SNDR is improved to 62.9 dB by ΔΣ assisted mode.

    本文言語English
    ホスト出版物のタイトルASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
    出版社Institute of Electrical and Electronics Engineers Inc.
    ページ317-318
    ページ数2
    2018-January
    ISBN(電子版)9781509006021
    DOI
    出版ステータスPublished - 2018 2 20
    イベント23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of
    継続期間: 2018 1 222018 1 25

    Other

    Other23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
    CountryKorea, Republic of
    CityJeju
    Period18/1/2218/1/25

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design

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