Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

Toshinori Numata, Ken Uchida, Junji Koga, Shin Ichi Takagi

    研究成果: Paper査読

    16 被引用数 (Scopus)

    抄録

    Device design issues regarding threshold voltage (Vth) control, short channel effects (SCE) and subthreshold slope are qantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (Vg2) and gate work function (Φm) control is found to provide superior SCE, Vth fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.

    本文言語English
    ページ179-180
    ページ数2
    DOI
    出版ステータスPublished - 2002 1 1
    イベントIEEE International SOI Conference - Williamsburg, VA, United States
    継続期間: 2002 10 72002 10 10

    Other

    OtherIEEE International SOI Conference
    国/地域United States
    CityWilliamsburg, VA
    Period02/10/702/10/10

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

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