Device design issues regarding threshold voltage (Vth) control, short channel effects (SCE) and subthreshold slope are qantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (Vg2) and gate work function (Φm) control is found to provide superior SCE, Vth fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.
|出版ステータス||Published - 2002 1 1|
|イベント||IEEE International SOI Conference - Williamsburg, VA, United States|
継続期間: 2002 10 7 → 2002 10 10
|Other||IEEE International SOI Conference|
|Period||02/10/7 → 02/10/10|
ASJC Scopus subject areas