Dynamic deficit round-robin scheduler for 5-Tb/s switch using wavelength routing

K. Yamakoshi, E. Oki, N. Yamanaka

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

A dynamic deficit round-robin (DDRR) scheduling scheme for a 5-Tb/s switch is proposed. DDRR is a DRR-based packet scheduler and it can satisfy the max-min fair share. However, DRR cannot satisfy both high throughput and delay requirements. DDRR resolves the problem by changing the granularity for deficit counters according to the packet lengths at queue heads. Simulation results showing the efficiency of DDRR are presented and an implementation of DDRR for the switch is also described.

本文言語English
ホスト出版物のタイトルHPSR 2002 - Workshop on High Performance Switching and Routing
ホスト出版物のサブタイトルMerging Optical and IP Technologies, Proceedings
出版社IEEE Computer Society
ページ204-208
ページ数5
ISBN(印刷版)488552184X, 9784885521843
DOI
出版ステータスPublished - 2002 1 1
外部発表はい
イベント2002 Workshop on High Performance Switching and Routing: Merging Optical and IP Technologies, HPSR 2002 - Kobe, Japan
継続期間: 2002 5 262002 5 29

出版物シリーズ

名前IEEE International Conference on High Performance Switching and Routing, HPSR
ISSN(印刷版)2325-5595
ISSN(電子版)2325-5609

Other

Other2002 Workshop on High Performance Switching and Routing: Merging Optical and IP Technologies, HPSR 2002
CountryJapan
CityKobe
Period02/5/2602/5/29

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

フィンガープリント 「Dynamic deficit round-robin scheduler for 5-Tb/s switch using wavelength routing」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル