抄録
A dynamic deficit round-robin (DDRR) scheduling scheme for variable-length packets is proposed. It can resolve the drawback of the conventional deficit round-robin (DRR) scheduler that short-packet delay performance and high throughput cannot be satisfied simultaneously. DDRR uses an adaptive granularity for the deficit counter, where the granularity is dynamically changed according to packet lengths is queues. The algorithm, along with the simulation results showing the efficiency, are presented. The DDRR scheduler was implemented for 5 Tbit/s switching system.
本文言語 | English |
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ページ(範囲) | 148-149 |
ページ数 | 2 |
ジャーナル | Electronics Letters |
巻 | 38 |
号 | 3 |
DOI | |
出版ステータス | Published - 2002 1月 31 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学