Energy-efficient dynamic instruction scheduling logic through instruction grouping

Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura

研究成果: Article査読

抄録

Dynamic instruction scheduling logic is quite complex and dissipates significant energy in microprocessors that support superscalar and out-of-order execution. We propose a novel microarchitectural technique to reduce the complexity and energy consumption of the dynamic instruction scheduling logic. The proposed method groups several instructions as a single issue unit and reduces the required number of ports and the size of the structure. This paper describes the microarchitecture mechanisms and shows evaluation results for energy savings and performance. These results reveal that the proposed technique can greatly reduce energy with almost no performance degradation, compared to the conventional dynamic instruction scheduling logic.

本文言語English
論文番号4814485
ページ(範囲)848-852
ページ数5
ジャーナルIEEE Transactions on Very Large Scale Integration (VLSI) Systems
17
6
DOI
出版ステータスPublished - 2009 6
外部発表はい

ASJC Scopus subject areas

  • ソフトウェア
  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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