Enforcing dimension-order routing in on-chip torus networks without virtual channels

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In the case of simple tile-based architecture, such as small reconfigurable processor arrays, a virtual-channel mechanism, which requires additional logic and pipeline stages, will be one of the crucial factors for a low cost implementation of their on-chip routers. To guarantee deadlock-free packet transfer with no virtual channels on tori, we propose a non-minimal strategy consistent with the rule of dimension-order routing (DOR) algorithm. Since embedded streaming applications usually generate predictable data traffic, the path set can be customized to the traffic from alternative DOR paths. Although the proposed strategy does not use any virtual channels, it achieves almost the same performance as virtual-channel routers on tori in eleven of 18 application traces.

本文言語English
ホスト出版物のタイトルParallel and Distributed Processing and Applications - 4th International Symposium, ISPA 2006, Proceedings
編集者Minyi Guo, Laurence T Yang, Beniamino Di Martino, Hans P. Zima, Hans P. Zima, Jack Dongarra, Feilong Tang
出版社Springer Verlag
ページ207-218
ページ数12
ISBN(印刷版)9783540680673
DOI
出版ステータスPublished - 2006
イベント4th International Symposium on Parallel and Distributed Processing and Applications, ISPA 2006 - Sorrento, Italy
継続期間: 2006 12月 42006 12月 6

出版物シリーズ

名前Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
4330
ISSN(印刷版)0302-9743
ISSN(電子版)1611-3349

Other

Other4th International Symposium on Parallel and Distributed Processing and Applications, ISPA 2006
国/地域Italy
CitySorrento
Period06/12/406/12/6

ASJC Scopus subject areas

  • 理論的コンピュータサイエンス
  • コンピュータ サイエンス(全般)

フィンガープリント

「Enforcing dimension-order routing in on-chip torus networks without virtual channels」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル