Enhanced degradation by negative bias temperature stress in Si nanowire transistor

Kensuke Ota, Masumi Saitoh, Chika Tanaka, Yukio Nakabayashi, Ken Uchida, Toshinori Numata

    研究成果: Article査読

    6 被引用数 (Scopus)

    抄録

    Negative bias temperature instability in Si nanowire transistors were systematically studied. Enhanced degradation by negative bias temperature (NBT) stress in narrow nanowire transistor was observed. Nanowire width and height dependences on threshold voltage shift suggest that the larger degradation was caused by the nanowire corner effect such as electric field concentration. High speed measurements elucidated the smaller recovery ratio in nanowire transistors which is attributed to be the local charge trap at nanowire corner. Stress memorization technique does not affect the threshold voltage shift by NBT stress.

    本文言語English
    論文番号02BC08
    ジャーナルJapanese journal of applied physics
    51
    2 PART 2
    DOI
    出版ステータスPublished - 2012 2 1

    ASJC Scopus subject areas

    • Engineering(all)
    • Physics and Astronomy(all)

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