Evaluation of a multicore reconfigurable architecture with variable core sizes

Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

A multicore architecture for processors has emerged as a dominant trend in the chip making industry. As reconfigurable devices gradually prove their capability in improving computation power while preserving flexibility, we are examining a multicore reconfigurable architecture consisting ofmultiple reconfigurable computational cores connected by an interconnection network. Using an NEe Electronics' DRP-l as a core for the multicore architecture, a comparison with a tile-based architecture is performed by implementing several streaming applications with various versions. By using wider communication channels and assigning more resources for computations, it is possible to improve throughput over implementations for the tile-based architecture. Another evaluation with different core sizes is examined in order to see the effect of core size in a homogeneous multicore system on performance and internal fragmentation. Evaluation results show that the size ofcore is a trade-offbetween throughput and resource usage.

本文言語English
ホスト出版物のタイトルIPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium
DOI
出版ステータスPublished - 2009 11 25
イベント23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009 - Rome, Italy
継続期間: 2009 5 232009 5 29

出版物シリーズ

名前IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium

Other

Other23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009
国/地域Italy
CityRome
Period09/5/2309/5/29

ASJC Scopus subject areas

  • 計算理論と計算数学
  • ハードウェアとアーキテクチャ
  • ソフトウェア

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