Evaluation of cache base network processor by using real backbone network trace

Shinichi Ishida, Michitaka Okuno, Hiroaki Nishi

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In this paper a novel cache-based packet-processing-engine (PPE) architecture that achieves high packet-processing throughput with low-power consumption is proposed and evaluated. As network packets of the same header information appear repeatedly in a short time, a special cache, the so called header-learning cache(HLC), memorizes the packet-processing method and enables most packets to skip the execution at the processing units array. The implementation of the cache-based PPE architecture, P-Gear, was designed. Real backbone network trace was used to evaluate the performance of it. This P-Gear can achieve over 80% cache hit rate using 4K/32K entry for access/core networks. Compared to conventional PPE, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.6% of the power consumption required by the conventional PPE.

本文言語English
ホスト出版物のタイトル2006 Workshop on High Performance Switching and Routing, HPSR 2006
出版社IEEE Computer Society
ページ49-54
ページ数6
ISBN(印刷版)0780395697, 9780780395695
DOI
出版ステータスPublished - 2006
イベント2006 Workshop on High Performance Switching and Routing, HPSR 2006 - Poznan, Poland
継続期間: 2006 6 72006 6 9

出版物シリーズ

名前2006 Workshop on High Performance Switching and Routing, HPSR 2006

Other

Other2006 Workshop on High Performance Switching and Routing, HPSR 2006
国/地域Poland
CityPoznan
Period06/6/706/6/9

ASJC Scopus subject areas

  • ソフトウェア
  • コンピュータ サイエンスの応用
  • 電子工学および電気工学
  • 理論的コンピュータサイエンス

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