Evaluation of MuCCRA-D: A dynamically reconfigurable processor with directly interconnected PEs

Masaru Kato, Yohei Hasegawa, Hideharu Amano

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Chips (SoCs). Interconnection in these architectures is one of the important factors to be evaluated. MuCCRA-1, the first prototype of MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project, uses a typical island-style interconnection in its PE array. Although the island-style interconnection is flexible, the large delay time caused by passing multiple switches and long wires often degrades its clock frequency. In this paper, MuCCRA-D, a dynamically reconfigurable processor which uses direct interconnection between neighboring PEs, is designed and evaluated. The evaluation results show that the required semiconductor area for MuCCRA-D is 12% smaller than that of MuCCRA-1 by reducing wiring resource in the interconnection. Since higher clock frequency can be used, DCT, α-Blending, Bubble-Sort and SHA-1 implemented on the MuCCRA-D are 3.84 times faster than MuCCRA-1 at maximum.

本文言語English
ホスト出版物のタイトルProceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
ページ215-221
ページ数7
出版ステータスPublished - 2008 12月 1
イベント2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 - Las Vegas, NV, United States
継続期間: 2008 7月 142008 7月 17

出版物シリーズ

名前Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008

Other

Other2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
国/地域United States
CityLas Vegas, NV
Period08/7/1408/7/17

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • ハードウェアとアーキテクチャ
  • ソフトウェア

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